Reducing Switching Activity on Datapath Buses with Control-Signal Gating

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 3, 1999, Pages 405-414

  Kapadia, Hema ^a,c,d,e   Benini, Luca ^a,b,e   De Micheli, Giovanni ^a,e  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE   (India)

^d University of Rochester   (United States)

^e Stanford University   (United States)

Author keywords

Clock gating; Control signal gating; Data buses; Datapaths; Logic synthesis; Low power; Power management; Switching activity

Indexed keywords

LOGIC DESIGN; OBSERVABILITY; SEQUENTIAL SWITCHING;

CLOCK GATING; CONTROL SIGNAL GATING; DATA BUSES;

COMPUTER ARCHITECTURE;

EID: 0033099452     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.748193     Document Type: Article

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