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Volumn 4, Issue 3, 2004, Pages 523-528

Simulation and experiments of stress migration for Cu/low-k BEoL

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CRACKS; DIELECTRIC MATERIALS; ELECTRIC CONDUCTIVITY; OPTICAL INTERCONNECTS; THERMAL STRESS; X RAY DIFFRACTION ANALYSIS;

EID: 11144236528     PISSN: 15304388     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDMR.2004.833225     Document Type: Article
Times cited : (37)

References (11)
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    • Ogawa, E.T.1
  • 2
    • 0037972839 scopus 로고    scopus 로고
    • Stress-Induced voiding and its geometry dependency characterization
    • K. Doong et al., "Stress-Induced voiding and its geometry dependency characterization," in Proc. IRPS, 2003, pp. 156-160.
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    • Doong, K.1
  • 3
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    • Geometrical aspects of stress-induced voiding in copper interconnects
    • A. von Glasow, A. H. Fisher, M. Hierlemann, and F. Ungar, "Geometrical aspects of stress-induced voiding in copper interconnects," in Proc. AMC, 2002, pp. 161-161.
    • (2002) Proc. AMC , pp. 161-161
    • Von Glasow, A.1    Fisher, A.H.2    Hierlemann, M.3    Ungar, F.4
  • 4
    • 84961734442 scopus 로고    scopus 로고
    • Effects of dielectric material and line width on thermal stresses of Cu line structures
    • D. Gan, G. Wang, and P. Ho, "Effects of dielectric material and line width on thermal stresses of Cu line structures," in Proc. IITC, 2002, pp. 271-273.
    • (2002) Proc. IITC , pp. 271-273
    • Gan, D.1    Wang, G.2    Ho, P.3
  • 5
    • 85001136039 scopus 로고    scopus 로고
    • Characterization of thermal stresses of Cu/low-k submicron interconnect structures
    • S. H. Rhee, Y. Du, and P. Ho, "Characterization of thermal stresses of Cu/low-k submicron interconnect structures," in Proc. IITC, 2001, pp. 89-91.
    • (2001) Proc. IITC , pp. 89-91
    • Rhee, S.H.1    Du, Y.2    Ho, P.3
  • 6
    • 18544402220 scopus 로고    scopus 로고
    • Microstructural characterization of inlaid copper interconnect lines
    • P. Besser et al., "Microstructural characterization of inlaid copper interconnect lines," J. Electron. Mater., vol. 30, no. 4, pp. 320-320, 2001.
    • (2001) J. Electron. Mater. , vol.30 , Issue.4 , pp. 320-320
    • Besser, P.1
  • 7
    • 0032137584 scopus 로고    scopus 로고
    • Finite element simulation of a stress history during the manufacturing process of thin film stacks in VLSI structures
    • J. Lee and A. Sauter Mack, "Finite element simulation of a stress history during the manufacturing process of thin film stacks in VLSI structures," IEEE Trans. Semicond. Manufact., vol. 11, pp. 458-465, 1998.
    • (1998) IEEE Trans. Semicond. Manufact. , vol.11 , pp. 458-465
    • Lee, J.1    Mack, A.S.2
  • 8
    • 0037972841 scopus 로고    scopus 로고
    • The effect of low-k ILD on the electromigration reliability of Cu interconnects with different line lengths
    • Hau-Riege, A. Marathe, and V. Pham, "The effect of low-k ILD on the electromigration reliability of Cu interconnects with different line lengths," in Proc. IRPS, 2002, pp. 173-177.
    • (2002) Proc. IRPS , pp. 173-177
    • Hau-Riege1    Marathe, A.2    Pham, V.3
  • 9
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    • Stress evolution due to electromigration in confined metal lines
    • M. A. Korhonen, R. D. Black, and C. Y. Li, "Stress evolution due to electromigration in confined metal lines," J. Appl. Phys., vol. 73, pp. 3790-3790, 1993.
    • (1993) J. Appl. Phys. , vol.73 , pp. 3790-3790
    • Korhonen, M.A.1    Black, R.D.2    Li, C.Y.3
  • 10
    • 0000594331 scopus 로고    scopus 로고
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  • 11
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    • Reimbold, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.