Finite element simulation of a stress history during the manufacturing process of thin film stacks in VLSI structures

IEEE Transactions on Semiconductor Manufacturing

Volumn 11, Issue 3, 1998, Pages 458-464

  Lee, Jin ^a   Mack, Anne Sauter ^a  

^a INTEL CORPORATION   (United States)

Author keywords

FEM analysis; Interconnection line; Intrinsic stress; Stress history; Thin film

Indexed keywords

ALUMINUM; COMPUTER SIMULATION; FINITE ELEMENT METHOD; SEMICONDUCTOR DEVICE STRUCTURES; STRESS ANALYSIS; THERMAL EXPANSION; THIN FILM DEVICES; TUNGSTEN; VLSI CIRCUITS;

INTRINSIC STRESS; STRESS HISTORY;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0032137584     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.705380     Document Type: Article

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