Design and InP HEMT technology for ultra-high speed digital ics with beyond 80-Gbit/s operation

Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

Volumn , Issue , 2004, Pages 211-214

  Suzuki, T ^a   Kawano, Y ^a   Nakasha, Y ^a   Takahashi, T ^a   Makiyama, K ^a   Hirose, T ^a   Takikawa, M ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

80 Gbit s; High speed digital circuit; InP HEMT

Indexed keywords

80 GBIT/S; INP HEMT; METAL-INSULATOR-METAL (MIM) CAPACITORS; TRANSISTOR VARIATION;

CAPACITORS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ELECTRODES; EVAPORATION; LOGIC GATES; MULTIPLEXING; SEMICONDUCTOR DEVICES; TRANSCONDUCTANCE; WIRELESS TELECOMMUNICATION SYSTEMS;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 10444278520     PISSN: 15508781     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSICS.2004.1392540     Document Type: Conference Paper

References (11)

1. M. Meghelli, "A 108Gb/s 4:1 Multiplexer in 0.13 μm SiGe-Bipolar Technology," IEEE ISSCC 2004 Digest paper, pp. 236-237.
2. Y. Suzuki, Y. Amamiya, Z. Yamazaki, S. Wada, H. Uchida, C. Kurioka, S. Tanaka, and H. Hida, "110Gb/s Multiplexing and Demultiplexing ICs," IEEE ISSCC 2004 Digest paper, pp. 232-233.
3. T. Suzuki, Y. Nakasha, T. Takahashi, K. Makiyama, T. Hirose, and M. Takikawa, "144-Gbit/s Selector and 100-Gbit/s 4:1 Multiplexer Using InP HEMTs," 2004 IEEE MTT-S Digest paper
4. Y. Yamashita et al., "Pseudomorphic In0.52Al0.48As/In0.7Ga0.3As HEMTs with an Ultrahigh fT of 562 GHz," IEEE Electron Device Letters, Vol. 23, No. 10, pp. 573-575, 2002.
5. T. Suzuki, T. Takahashi, K. Makiyama, K. Sawada, Y. Nakasha, T. Hirose, and M. Takikawa, "Under 0.5W 50Gb/s Full-Rate 4:1 MUX and 1:4 DEMUX in 0.13μm InP HEMT Technology," IEEE ISSCC 2004 Digest paper, pp. 234-235.
6. N. Hara, K. Makiyama, T. Takahashi, K. Sawada, T. Arai, T.Ohki, M. Nihei, T. Suzuki, Y. Nakasha, and M. Nishi, "Highly Uniform InAlAs/InGaAs HEMT Technology for High-speed Optical Communication System ICs," IEEE Trans. SEMICONDUCTOR MANUFACTURING, vol. 16, No3, pp 370, 2003.
7. K. Makiyama, T. Takahashi, T. Suzuki, K. Sawada, T. Ohki, M. Nishi, N. Hara and M. Takikawa, "Improvement of Circuit-Speed of HEMTs IC by Reducing the Parasitic Capacitance," IEEE Electron Device Meeting 2003, Technical Digest, 30.6.1.
8. Y. Nakasha, T. Suzuki, H. Kano, K. Tsukashima, A. Ohya, K. Sawada, K. Makiyama, M. Nishi, T. Hirose, M. Takikawa, and Y. Watanabe, "A 43-Gb/s Full-Rate-Clock 4:1 Multiplexer in InP-Based HEMT Technology," IEEE Journal of Solid-state Circuits, Vol. 37, No. 12, pp. 1703-1709 Dec. 2002.
9. T. Suzuki, Y. Nakasha, T. Sakoda, K. Sawada, T. Takahashi, K. Makiyama, T. Hirose, and M. Takigawa, "A 100-Gbit/s 2:1 Multiplexer in InP HEMT Technology," 2003 IEEE MTT-S Digest pp. 1173-1176.
10. Y. Nakasha, T. Suzuki, H. Kano, K. Kawano, T. Takahashi, K. Makiyama, K. Sawada, T. Hirose, and M. Takikawa, "An 80-Gbit/s 1:2 Demultiplexer in InP-based HEMT Technology," 2004 IEEE RFIC Digest paper.
11. T. Suzuki, T. Takahashi, T. Hirose, and M. Takigawa, "A 80-Gbit/s D-type Flip-flop Circuit Using InP HEMT Technology," 2003 IEEE GaAs IC Symposium Digest pp 165-168.