A simulation methodology for single-electron multiple-valued logics and its application to a latched parallel counter

IEICE Transactions on Electronics

Volumn E87-C, Issue 11, 2004, Pages 1818-1826

  Inokawa, Hiroshi ^a   Takahashi, Yasuo ^b   Degawa, Katsuhiko ^c   Aoki, Takafumi ^c   Higuchi, Tatsuo ^d  

^a NTT Basic Research Laboratories   (Japan)

^b HOKKAIDO UNIVERSITY   (Japan)

^c TOHOKU UNIVERSITY   (Japan)

^d TOHOKU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Analytical model; Counter; Multiple valued logic (MVL); Single electron transistor (SET); SPICE

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DATA REDUCTION; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; QUANTUM ELECTRONICS; SEMICONDUCTOR JUNCTIONS;

CONSTANT-VOLTAGE (CV) SOURCE; DRAIN CURRENT; LATCHED PARALLEL COUNTERS; SINGLE-ELECTRON-TRANSISTORS (SET);

TRANSISTORS;

EID: 10444270079     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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