Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E86-A, Issue 12, 2003, Pages 3009-3019

  Sakiyama, Jun ^a,c   Homma, Naofumi ^a   Aoki, Takafumi ^a   Higuchi, Tatsuo ^b  

^a TOHOKU UNIVERSITY   (Japan)

^b TOHOKU INSTITUTE OF TECHNOLOGY   (Japan)

^c JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

Circuit synthesis; Computer arithmetic algorithms; Datapath; Multipliers; Parallel counters; VLSI

Indexed keywords

ADDERS; ALGORITHMS; DATA REDUCTION; DIGITAL SIGNAL PROCESSING; FREQUENCY MULTIPLYING CIRCUITS; FUNCTIONS; OPTIMIZATION; SET THEORY; THRESHOLD LOGIC; TREES (MATHEMATICS); VLSI CIRCUITS;

CIRCUIT SYNTHESIS; COMPUTER ARITHMETIC ALGORITHMS; COUNTER TREE DIAGRAMS (CTD); DATAPATH; PARALLEL COUNTERS;

DIGITAL ARITHMETIC;

EID: 0842289050     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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