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Volumn 6, Issue 7, 2006, Pages 596-601

Copper Via Filling Electrodeposition of High Aspect Ratio Through Chip Electrodes Used for the Three Dimensional Packaging

Author keywords

Additives; Electrodeposition; Pulse Reverse Current; Three Dimensional Packaging; Through Chip Electrode; Via Filling

Indexed keywords


EID: 85009535675     PISSN: 13439677     EISSN: 1884121X     Source Type: Journal    
DOI: 10.5104/jiep.6.596     Document Type: Article
Times cited : (2)

References (7)
  • 2
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    • M. Tomisaka, H. Yonemura, M. Hoshino, and K. Takahashi:“Electroplating Cu Fulling Study for Thorough Electrode in Silicon Wafer of Three Dimensional LSI Chip Stacking”, Solid State Devices and Materials, Tokyo, 40, 2001.
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    • Tomisaka, M.1    Yonemura, H.2    Hoshino, M.3    Takahashi, K.4
  • 3
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    • 128Mbit NAND Flash Memory by Chip-on-Chip Technology with Cu Through Plug
    • T. Harada, K. Asao, K. Sasaki and Y. Kami:“128Mbit NAND Flash Memory by Chip-on-Chip Technology with Cu Through Plug”, 2001 ICEP Proceedings, pp. 39-44, 2001.
    • (2001) ICEP Proceedings , pp. 39-44
    • Harada, T.1    Asao, K.2    Sasaki, K.3    Kami, Y.4
  • 4
    • 0017935798 scopus 로고
    • A New Voltammetric Stripping Method Applied to the Determination of the Brightener Concentration in Copper Pyrophosphate Plating Bath
    • D. Tench and C. Ogden:“A New Voltammetric Stripping Method Applied to the Determination of the Brightener Concentration in Copper Pyrophosphate Plating Bath”, J. Electrochem. Soc., Vol. 125, pp. 194-201, 1978.
    • (1978) J. Electrochem. Soc. , vol.125 , pp. 194-201
    • Tench, D.1    Ogden, C.2
  • 5
    • 0001310173 scopus 로고    scopus 로고
    • Electrochemical and Fill Studies of a Multicomponent Additive Package for Copper Deposition
    • P. Taephaisitphonge, Y. Cao, and A. C. West:“Electrochemical and Fill Studies of a Multicomponent Additive Package for Copper Deposition”, Vol. 148, C492-C500, 2001.
    • (2001) , vol.148 , pp. C492-C500
    • Taephaisitphonge, P.1    Cao, Y.2    West, A.C.3
  • 6
    • 0038355681 scopus 로고    scopus 로고
    • High Aspect Ratio Copper Via Fill Used for Three Dimensional Chip Stacking
    • Tokyo
    • K. Kondo, T. Okamura, J. J. Sun, M. Tomisaka, H. Yonemura, M. Hoshino and K. Takahashi:“High Aspect Ratio Copper Via Fill Used for Three Dimensional Chip Stacking”, 2002 ICEP, pp. 327-336, Tokyo, 2002.
    • (2002) ICEP , pp. 327-336
    • Kondo, K.1    Okamura, T.2    Sun, J.J.3    Tomisaka, M.4    Yonemura, H.5    Hoshino, M.6    Takahashi, K.7
  • 7
    • 85009541415 scopus 로고    scopus 로고
    • Role of Damascene Via Filling Additives-Morphology Evolution
    • K. Kondo, K. Hayashi, Z. Tanaka and N. Yamakawa:“Role of Damascene Via Filling Additives-Morphology Evolution”, ECS Proc, Vol. 2000-2008, pp. 76-81, 2002.
    • (2002) ECS Proc , vol.2000-2008 , pp. 76-81
    • Kondo, K.1    Hayashi, K.2    Tanaka, Z.3    Yamakawa, N.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.