Nanoimprint lithography process optimization for the fabrication of high electron mobility transistors

Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

Volumn 21, Issue 6, 2003, Pages 2783-2787

  Macintyre, D S ^a   Chen, Y ^b   Gourlay, D ^a   Boyd, E ^a   Moran, D ^a   Cao, X ^a   Elgaid, K ^a   Stanley, C R ^a   Thayne, I ^a   Thoms, S ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b RUTHERFORD APPLETON LABORATORY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EPITAXIAL GROWTH; GATES (TRANSISTOR); LITHOGRAPHY; OPTIMIZATION; POLYMERS; SEMICONDUCTING SILICON; TRANSCONDUCTANCE;

MICROELECTRONS; NANOIMPRINT LITHOGRAPHY;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0942267543     PISSN: 10711023     EISSN: None     Source Type: Journal    
DOI: 10.1116/1.1629719     Document Type: Conference Paper

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