Design of 50-nm vertical MOSFET incorporating a dielectric pocket

IEEE Transactions on Electron Devices

Volumn 51, Issue 1, 2004, Pages 158-161

  Donaghy, D ^a   Hall, S ^a   De Groot, C H ^b   Kunz, V D ^b   Ashburn, P ^b  

^a UNIVERSITY OF LIVERPOOL   (United Kingdom)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

Dielectric pocket; Short channel effects (SCEs); Si devices; Vertical MOSFET

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIELECTRIC DEVICES; LITHOGRAPHY;

DIELECTRIC POCKET; SHORT-CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0742304006     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.821378     Document Type: Article

References (12)

1. T. Schulz, W. Rosner, L. Risch, A. Korbel, and U. Langmann, "Short channel vertical sidewall MOSFETs," IEEE Trans. Electron Devices, vol. 48, pp. 1783-1788, Aug. 2001.
2. V. R. Rao, F. Wittmann, H. Gossner, and I. Eisele, "Hysteresis behavior in 85-mm channel length n-MOSFETs grown by MBE," IEEE Trans. Electron Devices, vol. 43, pp. 973-976, June 1996.
3. J. Moers, D. Klaes, A. Tonnesmann, L. Vescan, S. Wickenhauseer, M. Marso, P. Kordos, and H. Luth, "19 GHz vertical Si p-channel MOSFET," IEE Electron. Lett., vol. 35, pp. 239-240, 1999.
4. J. M. Hergenrother et al., "The vertical replacement-gate (VRG) MOSFET: A 50 nm MOSFET with lithography-independent gate length," in IEDM Tech. Dig., 1999, pp. 75-78.
5. K. C. Liu, T. Chin, Q. Z. Lui, T. Nakamura, P. Yu, and P. Asbeck, "A deep submicron Si/sub 1-x/Ge/sub/sub x/Si vertical PMOSFET fabricated by Ge ion implantation," IEEE Electron Device Lett., vol. 19, pp. 13-15, Jan. 1998.
6. A. C. Lamb, L. S. Riley, S. Hall, V. D. Kunz, C. H. de Groot, and P. Ashburn, "A 50 nm vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket," in Proc. ESSDERC, 2000, pp. 347-350.
7. D. Donaghy, S. Hall, V. D. Kunz, C. H. de Groot, and P. Ashburn, "Investigating 50 nm channel length vertical MOSFETS containing a dielectric pocket in a circuit environment," in Proc. ESSDERC, 2002, pp. 499-503.
8. M. Jurczak, T. Skotniki, R. Gwoziecki, M. Paoli, B. Tormen, P. Tormen, P. Ribot, D. Dutartre, S. Monfay, and J. Galvier, "Dielectric pockets - A new concept of the junctions for deca-nanometric CMOS device," IEEE Trans. Electron Devices, vol. 48, pp. 1770-1774, Aug. 2001.
9. V. D. Kunz, T. Uchino, C. H. de Groot, P. Ashburn, D. C. Donaghy, S. Hall, Y. Wang, and P. Hemment, "Reduction of parasitic capacitance in vertical MOSFETs by fillet local oxidation (FILOX)," IEEE Trans. Electron Devices, vol. 50, pp. 1480-1487, June 2003.
10. F. Sato, T. Hashimoto, and T. Tashiro, "Sub-20 ps ECL circuits with high performance super self-aligned selectively grown SiGe base bipolar transistors," IEEE Trans. Electron Devices, vol. 42, pp. 483-488, Mar. 1995.
11. M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch, and M. Hirose, "Physically-based threshold voltage determination for MOSFETs of all gate lengths," IEEE Trans. Electron Devices, vol. 46, pp. 1429-1434, July 1999.
12. T. Skotniki, "Heading for decananometer CMOS - Is navigation among icebergs still a viable strategy?," in Proc. ESSDERC, 2000, pp. 19-33.