A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket

European Solid-State Device Research Conference

Volumn , Issue , 2001, Pages 347-350

  Lamb, A C ^a   Riley, L S ^a   Hall, S ^a   Kunz, V D ^b   De Groot, C H ^b   Ashburn, P ^b  

^a UNIVERSITY OF LIVERPOOL   (United Kingdom)

^b UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

VERTICAL MOSFETS;

EID: 84907501563     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2001.195272     Document Type: Conference Paper

References (4)

1. M. Jurczak et al., "Dielectric pockets: a new concept of the junctions for deca-nanometric CMOS devices", Proc. ESSDERC 2000, p. 536-539.
2. H. Gossner, I. Eisele and L. Risch "Vertical Si-Metal-Oxide-Semiconductor Field Effect Transistors with Channel Lengths of 50nm by Molecular Beam Epitaxy", Jpn. J. Appl. Phys. Vol. 33, April, 1994, pp. 2423-2428.
3. M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch and M. Hirose "Physically-Based Threshold Voltage Determination for MOSFET's of All Gate Lengths", IEEE Transactions on Electron Devices, Vol. 46, No. 7, 1999, pp. 1429-1434.
4. K. C. Liu, S. K. Ray, S. K. Oswal and S. K. Banerjee "A Deep Submicron Si1-xGex/Si Vertical PMOSFET Fabricated by Ge Ion Implantation", IEEE Electron Device Letters Vol. 19, No1, 1998, pp. 13-15.