Test and debug of networking SoCs - a case study

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 121-126

  Bommireddy, A ^a   Khare, J ^a   Shaikh, S ^a   Su, S T ^a  

^a Level One Communications   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; PHASE LOCKED LOOPS; QUEUEING NETWORKS; RANDOM ACCESS STORAGE; SWITCHING NETWORKS;

ETHERNET PORTS; MEDIA ACCESS CONTROLLERS; NETWORKING SYSTEM ON CHIP;

MICROPROCESSOR CHIPS;

EID: 0033742636     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (6)