Do chip size limits exist for DCA?

Proceedings - International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces

Volumn , Issue , 1999, Pages 150-157

  Schubert, A ^a   Dudek, R ^a   Leutenbauer, R ^a   Doring R ^a   Kloeser, J ^a   Oppermann, H ^a   Michel, B ^a   Reichl, H ^a   Baldwin, D ^b   Qu, J ^b   Sitaraman, S ^b   Swaminathan, M ^b   Wong, C P ^b   Tummala, R ^b  

^a FRAUNHOFER IZM   (Germany)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CREEP TESTING; FAILURE (MECHANICAL); INTERFACES (MATERIALS); PACKAGING MATERIALS; RELIABILITY; THERMAL EXPANSION;

FLIP CHIP APPLICATIONS; OPERATING PARAMETERS; OPTIMUM COMBINATION; PROPERTY REQUIREMENTS; SOLDER JOINT FATIGUE; STRUCTURE RELIABILITY; THERMAL EXPANSION MISMATCH; THERMOMECHANICAL RELIABILITY;

FLIP CHIP DEVICES;

EID: 0343917082     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISAPM.1999.757303     Document Type: Conference Paper

References (15)

1. K. Ramakrishna, Z. Johnson, "Effect of material and design parameters on the stresses induced in a Direct-Chip-Attach package during underfill cure", InterPack '97, June 15-19, 1997, Mauna Lani, Hawaii, USA, Proc. pp. 1639-1646.
2. V. Gektin, A. Bar-Cohen, S. Witzman, "Coffin-Manson based fatigue analysis of underfilled DCA", InterPack '97, June 15-19, 1997, Mauna Lani, Hawaii, USA, Proc. pp. 1655-1661.
3. A. Schubert, R. Dudek, R. Doling, "Reliability investigations of flip chip interconnects in FCOB and FCOG applications by FEA", 2nd Electronics Packaging Technology Conference, December 8-10, 1998, Singapore, Proc. pp. 49-56.
4. C. A. Le Gall, J. Qu, D. L. McDowell, "Thermomechanical stresses in an underfilled flip chip DCA", 3rd Intern. Symposium and Exihibition on Advanced Packaging Materials", March 9-12, 1997, Braselton, Georgia, Proc. pp. 128-129.
5. E. Jan Vardaman, Frank J. Bachner, "The NETPACK Roadmap: A European perspective on semiconductor packaging and assembly", TechSearch International, Inc., Austin, Texas, May 1998.
6. J. Kloeser et al., "Low cost bumping by stencil printing: process qualification for 200 urn pitch", MAPS Conference, San Diego, USA, 1998, Proc.
7. A. Ostmann, J. Kloeser, R. Aschenbrenner, H. Reichl, "Strategies for low cost flip chip assembly", ITAB Symposium, Sunnyvale, USA, 1998, Proc.
8. F. Stepniak: Solder flip chips employing electroless nickel: an evaluation of reliability and cost", Advances in Electronic Packaging, 1997, volume 1.
9. R. Dudek, M. Scherzer, A. Schubert, B. Michel, "FE-simulation for polymeric packaging materials", IEEE Trans. Comp., Packag., Manufact. Technol-Part A, vol. 21, no. 2, (June 1998), pp. 301-309.
10. A. Schubert, R. Dudek, D. Vogel, B. Michel, H. Reichl, "Materials mechanics and mechanical reliability of flip chip assemblies on organic substrates", Advancing Microelectronics, vol. 24, no. 4, July/August 1997, pp. 29-32.
11. R Dudek, M. Nylen, A. Schubert, B. Michel, H. Reichl, "An efficient approach to predict solder fatigue life and its application to SM- and area array components", Proc. of ECTC'47, San Jose, USA, May 1997, pp. 462-471.
12. A. Schubert, R. Dudek, J. Auersperg, D. Vogel, B. Michel, H. Reichl, "Thermo-mechamcal reliability analysis of flip chip assemblies by combined microDAC and the finite element method", InterPack '97, June 15-19, 1997, Mauna Lani, Hawaii, USA, Proc. pp. 1647-1654.
13. C. A. Le Gall, J. Qu, D. L. McDowell, "Delamination cracking in encapsulated flip chips", Proc. 46th Electronic Components and Technology Conference 1996, Orlando, USA, May 1996, pp. 430-434.
14. Goh, Teck Joo, "Parametric finite element Analysis of solder joint reliability of flip chip on board", 2nd Electronics Packaging Technology Conference, December 8-10, 1998, Singapore, Proc. pp. 57-62.
15. St. Michaelides, S. Sitaraman, "Role of underfilling imperfections on flip-chip reliability", InterPack '97, June 15-19, 1997, Mauna Lani, Hawaii, USA, Proc. pp. 1487-1493.