A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact

IEEE Transactions on Electron Devices

Volumn 49, Issue 8, 2002, Pages 1462-1468

  Fujishima, Naoto ^b   Sugi, Akio ^c   Kajiwara, Satomi ^c   Matsubara, Kunio ^c   Nagayasu, Yoshihiko ^c   Salama, C Andre T ^a,b  

^a IEEE

^b UNIVERSITY OF TORONTO   (Canada)

^c FUJI ELECTRIC CO   (Japan)

Author keywords

Miller capacitance; On resistance; Power MOSFET; Trench

Indexed keywords

CAPACITANCE MEASUREMENT; CHARACTERIZATION; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC RESISTANCE MEASUREMENT; FABRICATION; GATES (TRANSISTOR); MASKS; POWER ELECTRONICS; SEMICONDUCTOR DEVICE STRUCTURES; SWITCHING NETWORKS; TRANSMISSION ELECTRON MICROSCOPY;

DEVICE PITCH; MILLER CAPACITANCE; TRENCH BOTTOM DRAIN CONTACT; TRENCH BOTTOM SOURCE CONTACT;

MOSFET DEVICES;

EID: 0036683906     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.801434     Document Type: Article

References (12)

1. A new concept for the lateral DMOS transistor for smart power ICs
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5. A high density, low on-resistance, trench lateral power MOSFET with a trench bottom source contact
6. A new vertical power MOSFET structure with extremely reduced on-resistance
7. A 0.35 μm CMOS based smart power technology for 7 V-50 V applications