Simulation study on comparison between metal gate and polysilicon gate for sub-quarter-micron MOSFET's

IEEE Electron Device Letters

Volumn 20, Issue 12, 1999, Pages 632-634

  Abe, Yuji ^a   Oishi, Toshiyuki ^a   Shiozawa, Katsuomi ^a   Tokuda, Yasunori ^a   Satoh, Shinichi ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); THRESHOLD VOLTAGE;

GATE DEPLETION; METAL GATES; POLYSILICONS;

MOSFET DEVICES;

EID: 0033324081     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.806111     Document Type: Article

References (8)

1. Y. Taur, D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S.-H. Lo, G. A. Sai-Halasz, R. G. Viswanathan, H.-J. C. Wann, S. J. Wind, and H.-S. Wong, "CMOS scaling into the nanometer regime," Proc. IEEE, vol. 85, p. 486, 1997.
2. L. Dori, A. Megdanis, S. B. Brodsky, M. Arienzo, and S. A. Cohen, "Sputtered tungsten for deep submicron complementary metal-oxide-semiconductor technology," Thin Solid Films, vols. 193/194, p. 501, 1990.
3. S. Kimura, J. Tanaka, H. Noda, T. Toyabe, and S. Ihara, "Short-channel-effect-suppressed sub-0.1 μm grooved-gate MOSFET's with W gate," IEEE Trans. Electron Devices, vol. 42, p. 94, Jan. 1995.
4. K. T. Kim, L. G. Kang, T. S. Park, Y. S. Shin, J. K. Park, C. J. Lee, C. G. Hwang, D. Chin, and Y. E. Park, "Tungsten suicide/titanium nitride compound gate for submicron CMOSFET," in Proc. IEEE Symp. VLSI Technology, 1990, p. 115.
5. J. C. Hu, H. Yang, R. Kraft, A. L. P. Potondaro, S. Hattangady, W. W. Lee, R. A. Chapman, C.-P. Chao, A. Chatterjee, M. Hanratty, M. Rodder, and L-C. Chen, "Feasibility of using W/TiN as metal gate for conventional 0.13 μm CMOS technology and beyond," in IEDM Tech. Dig., 1997, p. 825.
6. G. J. Hu and R. H. Bruce, "Design tradeoffs between surface and buried-channel FET's," IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985.
7. M. Rodder, M. Hanratty, D. Rogers, T. Laaksonen, J. C. Hu, S. Murtaza, C.-P. Chao, S. Hattangady, S. Aur, A. Amerasekera, and I.-C. Chen, "A 0.10 μm gate length CMOS technology with 30 Å gate dielectric for 1.0 V-1.5 V applications," in IEDM Tech. Dig., 1997, p. 223.
8. M. Rodder, I.-C. Chen, S. Hattangady, and J. C. Hu, "Scaling to a 1.0 V-1.5 V, sub 0.1 μm gate length CMOS technology: Perspective and challenges," in Ext. Abst. Conf. Solid State Devices and Materials, 1998, p. 158.