Synthesis of arithmetic circuits considering layout effects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 11, 2003, Pages 1487-1503

  Um, Junhyung ^a   Kim, Taewhan ^b  

^a SAMSUNG Electronics   (South Korea)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Arithmetic circuit; Carry save adder (CSA); Layout aware synthesis; Timing optimization

Indexed keywords

ADDERS; ALGORITHMS; DIGITAL ARITHMETIC; MATHEMATICAL MODELS; OPTIMIZATION;

ARITHMETIC CIRCUITS; CARRY SAVE ADDER; SYSTEM ON CHIP DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242636383     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.818301     Document Type: Article

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