A practical approach to the synthesis of arithmetic circuits using carry-save-adders

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 5, 2000, Pages 615-624

  Kim, Taewhan ^a   Urn, Junhyung ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Arithmetic circuit; Circuit optimization; Rtl synthesis; Timing

Indexed keywords

ADDERS; ALGORITHMS; CARRY LOGIC; COMPUTATIONAL METHODS; COMPUTER AIDED LOGIC DESIGN; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION;

ARITHMETIC CIRCUIT; CARRY SAVE ADDER; REGISTER TRANSFER LEVEL SYNTHESIS;

LOGIC CIRCUITS;

EID: 0033704879     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.845087     Document Type: Article

References (24)

1. D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis-Introduction to Chip and System Design. Norwell, MA: Kulwer Academic, 1992.
2. M. Potkonjak and J. RabaeyOptimizing resource utilization using transformations," in Proc. Int. Conf. Computer-Aided Design, 1991, pp. 88-91.
3. _Maximally fast and arbitrarily fast implementation of linear computations," in Proc. Int. Conf. Computer-Aided Design, 1992, pp. 304-308.
4. D. Lobo and B. PangrleRedundant operation creation: A scheduling optimization technique," in Proc. Design Automation Conf., 1991, pp. 775-778.
5. A. Nicolau and R. PotasmaIncremental tree height reduction for highlevel synthesis," in P roc. Design Automation Conf., 1991, pp. 770-774.
6. R. Hartley and A. E. CasavantTree-height minimization in pipelined architectures," in Proc. Int. Conf. Computer-Aided Design, 1989, pp. 112-115.
7. _Optimized pipelined networks of associative and commutative operators," IEEE Trans. Computer-Aided Design, vol. 13, Nov. 1994.
8. K. K. ParhiHigh-level algorithm and architecture transformations for DSP synthesis,"/ VLSI Signal Processing, pp. 121-143, 1995.
9. M. Janssens, F. Catthoor, and H. De ManA specification invariant technique for operation cost minimization in flow-graphs," in Proc. 7th Int. Symp. High-Level Synthesis, 1994, pp. 146-151.
10. _A specification invariant technique for regularity improvement between flow-graph clusters," in Proc. Eur.Design Automation Conf., 1996, pp. 138-143.
11. J. Urn and T. KimUtilization of carry-save-adders in arithmetic optimization," in Proc. 12th Int. AS1C/SOC Conf., 1999, pp. 173-177.
12. R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Norwell, MA: Kulwer Academic, 1984.
13. R. K. Brayton, R. Rudell, A. L. Sangiovanni-Vincentelli, and A. R. WangMIS: A multiple-level logic optimization systems," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1062-1082, Nov. 1987.
14. J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, and Y. WatanabeA delay model for logic synthesis of continuously-sized networks," in Proc. IEEE Int. Conf. Computer-Aided Design, 1995, pp. 458-462.
15. S. S. Sapatnekar and W. ChuangPower vs. delay in gate sizing: Conflicting objectives?," in Proc. IEEE Int. Conf. Computer-Aided Design, 1995, pp. 463-466.
16. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design-A Systems Perspective. Reading, MA: Addison-Wesley, 1985.
17. T. Kim, W. Jao, and S. TjiangCircuit optimization using carry-saveadder cells," IEEE Trans. Compute r-Aided Design, vol. 17, pp. 974-984, Oct. 1998.
18. DesignWare Components Databook, Synopsys Inc., Mountain View, CA, 1996.
19. Design Compiler Manual, Synopsys Inc., Mountain View, CA, 1998.
20. Behavioral Compiler Manual. Mountain View, CA: Synopsys Inc., 1998.
21. VHDL Users Guide, Synopsys Inc., Mountain View, CA, 1997.
22. GlO-p Cell-Based ASIC Product Databook, LSI Logic Inc., Milpitas, CA, 1996.
23. A. C. Parker, J. Pizarro, and M. J. MlinarMAHA: A program for datapath synthesis," in Proc. IEEE Design Automation Conf., 1986, pp. 461-466.
24. P. Paulin and J. KnightHigh-level synthesis benchmark results using a global scheduling algorithm," in Logic and Architecture Synthesis for Silicon Compilers. Amsterdam, The Netherlands: North-Holland, 1898, pp. 211-228.