Improved merging of datapath operators using information content and required precision analysis

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 462-467

  Mathur, Anmol ^a   Saluja, Sanjeev ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; BIT ERROR RATE; DATA FLOW ANALYSIS; MATHEMATICAL TRANSFORMATIONS; SIGNAL RECONSTRUCTION;

DATA FLOW GRAPHS (DFG);

MERGING;

EID: 0034853851     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156184     Document Type: Article

References (8)

1. A method for the construction of minimum-redundancy codes
2. Arithmetic optimization using carry-save-adders
3. Computer arithmetic systems: Algorithms, architectures and implementations
4. Optimal allocation of carry-save-adders in arithmetic optimization
5. A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis
6. A suggestion for a fast multiplier
7. System level fixed-point design based on an interpolative approach