Use of test structures for characterization and modeling of inter- and intra-layer capacitances in a CMOS process

IEEE Transactions on Semiconductor Manufacturing

Volumn 10, Issue 2, 1997, Pages 233-241

  Nouet, Pascal ^a,b   Toulouse, Alain ^b  

^a IEEE   (France)

^b LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES;

ONCHIP MEASUREMENT METHODS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0031139438     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.572075     Document Type: Article

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