A rated-clock test method for path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 2, 1998, Pages 323-331

  Bose, Soumitra ^a,b   Agrawal, Prathima ^a,c   Agrawal, Vishwani D ^a,b  

^a IEEE   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c AT AND T LABS RESEARCH   (United States)

Author keywords

At speed testing; Delay test; Path delay fault; Test generation; Timing verification

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; SEQUENTIAL CIRCUITS; TIMING CIRCUITS; VECTORS;

PATH DELAY FAULT; TIMING VERIFICATION;

INTEGRATED CIRCUIT TESTING;

EID: 0032095266     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.678897     Document Type: Article

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