Testing high speed VLSI devices using slower testers

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 16-21

  Krstic, Angela ^a   Cheng, Kwang Ting ^a   Chakradhar, Srimat T ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; ERROR DETECTION; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; TEST FACILITIES; TIMING CIRCUITS;

AT-SPEED TESTING; FAULT COVERAGE; MULTIPLE INPUT PATTERNS; SLOWER TESTERS;

VLSI CIRCUITS;

EID: 0032639202     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (24)