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Volumn 2000-January, Issue , 2000, Pages 185-192

Tunable fault tolerance for runtime reconfigurable architectures

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; COMPUTERS; FAULT TOLERANCE; RECONFIGURABLE HARDWARE;

EID: 84949757980     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903405     Document Type: Conference Paper
Times cited : (8)

References (13)
  • 6
    • 84949874561 scopus 로고    scopus 로고
    • M. S. Thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University
    • M. Meyers, "Testing of Pipeline Reconfigurable Machines", M. S. Thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, 1998
    • (1998) Testing of Pipeline Reconfigurable Machines
    • Meyers, M.1
  • 7
  • 8
    • 0029700925 scopus 로고    scopus 로고
    • An approach for testing programmable/configurable field programmable gate arrays
    • W. K. Huang and F. Lombardi, "An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays", 14th IEEE VLSI Test Symposium, 1996
    • (1996) 14th IEEE VLSI Test Symposium
    • Huang, W.K.1    Lombardi, F.2
  • 9
    • 0029519091 scopus 로고
    • Universal test complexity of field-programmable gate arrays
    • Los Alamitos, CA
    • T. Inoue, et al., "Universal Test Complexity of Field-Programmable Gate Arrays", Fourth Asian Test Symposium, Los Alamitos, CA, 1995
    • (1995) Fourth Asian Test Symposium
    • Inoue, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.