On Test Data Volume Reduction for Multiple Scan Chain Designs

ACM Transactions on Design Automation of Electronic Systems

Volumn 8, Issue 4, 2003, Pages 460-469

  Reddy, Sudhakar M ^a   Miyasey, Kohei ^b   Kajihara, Seiji ^b   Pomeranz, Irith ^c  

^a UNIVERSITY OF IOWA   (United States)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Decompressor; Design for testability; Don't care identification; Encoding techniques; Test data compression

Indexed keywords

COMBINATORIAL CIRCUITS; DESIGN FOR TESTABILITY; LOGIC DESIGN; RELIABILITY; SEMICONDUCTOR DEVICE TESTING; SYSTEMS ANALYSIS;

DECOMPRESSOR CIRCUITS;

DATA REDUCTION;

EID: 0142031631     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/944027.944031     Document Type: Article

References (13)

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