Designing self-checking FPGAs through error detection codes

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 60-68

  Bolchini, C ^a   Salice, F ^a   Sciuto, D ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

Application specific integrated circuits; Circuit faults; Circuit synthesis; Combinational circuits; Design methodology; Electrical fault detection; Fault detection; Field programmable gate arrays; Logic functions; Network synthesis

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CODES (SYMBOLS); COMBINATORIAL CIRCUITS; DEFECTS; DESIGN FOR TESTABILITY; ELECTRIC FAULT LOCATION; ERRORS; FAULT DETECTION; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC SYNTHESIS; NETWORKS (CIRCUITS); SYNTHESIS (CHEMICAL); VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT SYNTHESIS; DESIGN METHODOLOGY; ELECTRICAL FAULT DETECTIONS; LOGIC FUNCTIONS; NETWORK SYNTHESIS;

ERROR DETECTION;

EID: 0141573048     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173502     Document Type: Conference Paper

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