Synthesis methodology aimed at improving the quality of TSC devices

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 247-255

  Bolchini, C ^a   Pomante, L ^a   Salice, F ^a   Sciuto, D ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT TESTING; QUALITY ASSURANCE;

TOTALLY SELF-CHECKING (TSC) COMBINATORIAL DEVICES;

COMBINATORIAL CIRCUITS;

EID: 0033312904     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)