Fault analysis for networks with concurrent error detection

IEEE Design and Test of Computers

Volumn 15, Issue 4, 1998, Pages 66-74

  Bolchini, Cristiana ^a,b   Salice, Fabio ^a,c   Sciuto, Donatella ^a,c,d,e,f  

^a POLITECNICO DI MILANO   (Italy)

^b VLSI Systems   (Japan)

^c IEEE

^d UNIVERSITY OF BRESCIA   (Italy)

^e BOCCONI UNIVERSITY   (Italy)

^f UNIVERSITY OF COLORADO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; ELECTRIC FAULT LOCATION; ENCODING (SYMBOLS); ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

CONCURRENT ERROR DETECTION; TOTALLY SELF-CHECKING (TSC) DESIGN METHODOLOGY;

INTEGRATED CIRCUIT TESTING;

EID: 0032181144     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.735929     Document Type: Review

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