Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET

Solid-State Electronics

Volumn 47, Issue 11, 2003, Pages 2131-2134

  Saxena, Manoj ^b   Haldar, Subhasis ^c   Gupta, Mridula ^a   Gupta, R S ^a  

^a UNIVERSITY OF DELHI   (India)

^b UNIVERSITY OF DELHI   (India)

^c UNIVERSITY OF DELHI   (India)

Author keywords

ASYMGAS; Carrier transport; DIBL; Efficiency; Gate stack

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FIELD EFFECTS; GATES (TRANSISTOR);

GATE STACKS;

MOSFET DEVICES;

EID: 0043231377     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00221-1     Document Type: Article

References (9)

1. Yu B., Ju D.H., Lee W.C., Kepler N., King T.J., Hu C. Gate engineering for deep-submicron CMOS transistors. IEEE Trans. Electron Dev. 45:1998;1253-1262.
2. Sanchez J.J., Hsueh K.K., DeMassa T.A. Drain-engineered hot-electron resistant device structures: a review. IEEE Trans. Electron Dev. 36(9):1989;1125-1132.
3. Wann C.H., Noda K., Tanaka T., Yoshida M., Hu C. A comparative study of advanced MOSFET concepts. IEEE Trans. Electron Dev. 43(10):1996;1742-1753.
4. Shin H., Lee S. An 0.1-μ m asymmetric halo by large-angle-tilt implant (AHLATI) MOSFET for high performance and reliability. IEEE Trans. Electron Dev. 46(4):1999;820-822.
5. Cheng B., Cao M., Rao R., Inani A., Voorde P.V., Greene W.M.et al. The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs IEEE Trans. Electron Dev. 46:1999;1537-1544.
6. Inani A., Rao R., Cheng B., Woo J. Gate stack architecture analysis and channel engineering in deep sub-micron MOSFETs. Jpn. J. Appl. Phys. 38(4B):1999;2266-2271.
7. Gusev E.P., Buchanan D.A., Cartier E., Kumar A., DiMaria D., Guha S.et al. Ultrathin high-K gate stacks for advanced CMOS devices IEDM Tech. Dig. 2001;451-454.
8. SILVACO International, ATLAS: 2D Device Simulator.
9. Suzuki K. Short channel MOSFET using a universal channel depletion width parameter. IEEE Trans. Electron Dev. 47:2000;1202-1208.