Leakage power reduction in low-voltage CMOS designs

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1998, Pages 167-173

  Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE CURRENTS; THRESHOLD VOLTAGE; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; POWER CONTROL;

DESIGN TECHNIQUE; DYNAMIC THRESHOLD; LEAKAGE POWER REDUCTION; LOW SUPPLY VOLTAGES; MULTIPLE-THRESHOLD VOLTAGE; SUBSTRATE BIASING; TRANSISTOR STACKING; WEAK INVERSION REGION;

ELECTRIC LOSSES; CMOS INTEGRATED CIRCUITS;

TRANSISTOR THRESHOLD VOLTAGE;

EID: 0032262096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.814856     Document Type: Conference Paper

References (22)

1. A. Keshavarzi, K. Roy, and C. Hawkins, "Intrinsic Iddq-Origins, Reduction, and Applications in Deep Sub-/j. Low-Power CMOS IC's," IEEE International Test Conference, 1997, pp. 146-155.
2. Y.P Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, New York, 1987.
3. J.R. Brews, Chap. 3 in, High Speed Semiconductor Devices, ed. S.M. Sze, John Wiley & Sons, New York,1990.
4. R. Pierret, Semiconductor Device Fundamentals, Addison-Wesley, Reading, MA, 1996.
5. M. Bohr, et al., "A High Performance 0.25 mm Logic Technology Optimized for 1.8 V Operation," IEDM Tech. Dig., pp. 847-851, Dec. 1996.
6. Jan M. Rabaey, "Digital Integrated Circuits," New Jersey: Prentice-Hall, 1996.
7. C. Hu, "Device and technology impact on low power electronics," in Low Power Design Methodologies,Kluwer, pp. 21-36, 1996.
8. Y. Ye, S. Borkar and V. De, "Standby Leakage Reduction in High-Performance Circuits Using Transistor Stack Effects," 1998 Symposium on VLSI Circuit, to appear.
9. Texas Instruments.
10. M.C. Johnson, K. Roy, and D. Somasekhar" A model for leakage control by transistor stacking", Technical Report TR-ECE 9712, Purdue University, Department of ECE.
11. J. Sheu, et. al., "BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors", IEEE J. Solid-State Circuits, SC-22, 1987.
12. M.-C. Jeng, "Design and Modeling of Deep-Submicrometer MOSFETS", Electronics Research Laboratory, Rep. No. ERL-M90/90, University of California, Berkeley, 1990.
13. "HSPICE User's Manual", Vol.II, 1996
14. Carlin Vieri, et al., "SOLAS: Dynamically Variable Threshold SOI with Active Substrate", IEEE Symposium on Low Power Electronics, pp. 86, 1995.
15. Shin'ichiroMutoh, et al., "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS", IEEE Journal of Solid-State Circuits, Vol.30, No.8, pp847, 1995
16. Takeshi Andoh, et al., "Design Methodology for Low Voltage MOSFETs", IEDM Tech. Dig., pp. 79,1994.
17. Fariborz Assaderaghi, et. al., "A Dynamic Threshold Voltage MOSFET(DTMOS) for Ultra-Low Voltage Operation", IEDM Tech. Dig., pp809, 1994.
18. L. Wei, Z. Chen, and K. Roy, "Double Gate Dynamic Threshold Voltage (DGDT) SOI MOSFETs for Low Power High Performance Designs," IEEE SOI Conference, 1997, pp. 82-83.
19. L. Wei, Z. Chen, and K. Roy, "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits," IEEE/ACM Design Automation Conference, 1998.
20. J.P. Denton and G.W. Neudeck."Fully depleted dual-gated thin-film SOI P-MOSFET's fabricated in SOI islands with an isolated buried polysilicon backgate," IEEE Electron Device Letters, v 17 n 11 Nov 1996. p 509-511.
21. P.C. Yeh, and J.G. Fossum,"Viable deep-submicron FD/SOI CMOS design for low-voltage applications," IEEE International SOI Conference 1994,pp.23-24.
22. M. Sachdev, "Deep Submicron IDDQ Testing: Issues and Solutions," European Des. & Test Conf., March 1997.