Static energy reduction techniques for microprocessor caches

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 276-283

  Hanson, H ^a   Hrishikesh, M S ^a   Agarwal, V ^a   Keckler, S W ^a   Burger, D ^a  

^a University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; ENERGY UTILIZATION; LEAKAGE CURRENTS; MODULATION; TRANSISTORS;

LOW-LEAKAGE TRANSISTORS;

MICROPROCESSOR CHIPS;

EID: 0035183730     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Design challenges of technology scaling
2. A static power model for architects
3. The future of wires
4. Cache-line decay: Exploiting generational behavior to reduce leakage power
5. An autobackgate-controlled MT-CMOS circuit
6. t and copper interconnects
7. A low power SRAM using auto-backgate-controlled MT-CMOS
8. dd: A circuit technique to reduce leakage in deep-submicron cache memories
9. Leakage power reduction in low-voltage CMOS designs
10. An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance caches
11. Adaptive mode-control: A static-power-efficient cache design