On test coverage of path delay faults

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 418-421

  Majhi, Ananta K ^a   Jacob, James ^a   Patnaik, Lalit M ^a   Agrawal, Vishwani D ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ERROR DETECTION; FAILURE ANALYSIS; ITERATIVE METHODS; LOGIC CIRCUITS;

PATH DELAY FAULTS; TWO PASS TEST GENERATION METHOD;

INTEGRATED CIRCUIT TESTING;

EID: 0029713594     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)