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Volumn , Issue , 1996, Pages 418-421
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On test coverage of path delay faults
a
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Author keywords
[No Author keywords available]
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Indexed keywords
COMBINATORIAL CIRCUITS;
COMPUTATIONAL COMPLEXITY;
COMPUTER SIMULATION;
ERROR DETECTION;
FAILURE ANALYSIS;
ITERATIVE METHODS;
LOGIC CIRCUITS;
PATH DELAY FAULTS;
TWO PASS TEST GENERATION METHOD;
INTEGRATED CIRCUIT TESTING;
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EID: 0029713594
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (19)
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References (11)
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