Advantages of p++ polysilicon etch stop layer versus p++ silicon

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5116 II, Issue , 2003, Pages 699-709

  Charavel, Rémy ^a   Laconte, Jean ^a   Raskin, Jean Pierre ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

Buried mask; Polysilicon p++; Roughness; Selectivity; Silicon p++; TMAH etching

Indexed keywords

CMOS INTEGRATED CIRCUITS; MICROELECTROMECHANICAL DEVICES; PHOTOLITHOGRAPHY; SILICON WAFERS; SOLUBILITY;

BORON IMPLANT; WAFER BONDING;

POLYSILICON;

EID: 0042329333     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.498107     Document Type: Conference Paper

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