Flip-chip BGA design to avert die cracking

Journal of Electronic Packaging

Volumn 123, Issue 1, 2001, Pages 58-63

  Han, J B ^a  

^a AGILENT TECHNOLOGIES   (Singapore)

Author keywords

Ball Grid Array (BGA); Crack; Design Methodology; Design of Experiment (DOE); Die; Finite Element Analysis (FEA); Flip Chip; Fracture Mechanics

Indexed keywords

EID: 0040621790     PISSN: 10437398     EISSN: None     Source Type: Journal    
DOI: 10.1115/1.1329130     Document Type: Article

References (20)

1. Mathieu, B., and Dasgupta, A., 1994, "A Fractional-Factorial Numerical Technique for Stress Analysis of Glass-to-Metal Lead Seals," ASME J. Electron. Packag., 116, pp. 98-104.
2. Jih, E., and Pao, Y.-H., 1995, "Evaluation of Design Parameters for Leadless Chip Resistors Solder Joints," ASME J. Electron. Packag., 117, pp. 94-117.
3. Mertol, A., 1995, "Application of the Taguchi Method on the Robust Design of Molded 225 Plastic Ball Grid Array Packages," IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 18, pp. 734-743.
4. Mertol, A., 1997, "Optimization of High Pin Count Cavity-up Enhanced Plastic Ball Grid Array (EPBGA) Packages for Robust Design," IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 20, pp. 376-388.
5. Yeh, C.-P., Zhou, W. X., and Wyatt, K., 1996, "Parametric Finite Element Analysis of Flip Chip Reliability," Int. J. Microcircuits Electron. Packag., 19, pp. 120-127.
6. Villani, A., and Hsu, S. C., 1996, "Reliablity of Low Cost Copper Heat Spreader Pin Grid Array Ceramic Packages," Int. J. Microcircuits Electron. Packag., 19, pp. 138-145.
7. Pecht, M. G., 1998, "Virtual Product Development," IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 21, p. 610.
8. Lindell, M., Stoaks, P., Carey, D., and Sandborn, P., 1998, "The Role of Physical Implementation in Virtual Prototyping of Electronic Systems, IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 21, pp. 611-616.
9. Evans, T. C., 1999, "Future Packaging Reliability Test," HDP/MCM-1999 Proceedings, Denver, Colorado, pp. 389-394.
10. Chin, S.-W., Rajan, S. D., Nagaraj, B. K., and Mahalingam, M., 1994, "Automated Design Tool for Examining Microelectronic Packaging Design Alternatives," IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 17, pp. 76-82.
11. Broek, D., 1982, Elementary Engineering Fracture Mechanics, Martinus Nijhoff, Boston.
12. Van Vroonhoven, J. C. W., 1993, "Effects of Adhesion and Delamination on Stress Singularities in Plastic-Packaged Integrated Circuits," ASME J. Electron. Packag., 115, pp. 28-33.
13. Hu, K. X., Yen, C. P., Wu, X. S., and Wyatt, K., 1996, "An Interfacial Delamination Analysis for Multichip Module Thin Film Interconnects," ASME J. Electron. Packag., 118, pp, 206-213.
14. Sato, M., Yoshioka, S., Inoue, A., Tani, S., and Iwaoka, M., 1997, "Analysis of Delamination Arrest Effect of Dimples on Interface in LSI Package," JSME Int. J., Ser. A, 40, pp. 58-64.
15. Fan, X. J., Teo, Y. C., Teo, P. S., and Lim, T. B., 1998, "Die Cracking Analysis in Flip Chip PBGA," Proceedings of the Third International Symposium on Electronic Packaging Technology, Beijing, China, pp. 458-463.
16. Liu, X. K., Suo, Z., and Ma, Q., 1999, "Split Singularities: Stress Field Near the Edge of a Silicon Die on a Polymer Substrate," Acta Mater., 47, pp. 67-76.
17. Liu, X. K., Suo, Z., Ma, Q., and Fujimoto, H., 2000, "Developing Design Rules to Avert Cracking and Debonding in Integrated Circuit Structures," Eng. Fract. Mech., 66, pp. 387-402.
18. Wang, J., Qian, Z., and Liu, S., 1998, "Process Induced Stresses of a Flip-Chip Packaging by Sequential Processing Modeling Technique," ASME J. Electron. Packag., 120, pp. 309-313.
19. Owen, D. R. J., and Fawkes, A. J., 1983, Engineering Fracture Mechanics: Numerical Methods and Applications, Pineridge Press, Swansea, UK.
20. Lee, T. W., and Pabbisetty, S. V., eds., 1993, Microelectornic Failure Analysis: Desk Reference, 3rd Ed., ASM International (The Material Information Society), Materials Part, OH, p. 366.