Implementation of low-power FFT processor cores using a novel order-based processing scheme

IEE Proceedings: Circuits, Devices and Systems

Volumn 150, Issue 3, 2003, Pages 149-154

  Hasan, M ^a   Arslan, T ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; CALCULATIONS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FAST FOURIER TRANSFORMS; LOGIC GATES; SEMICONDUCTING SILICON;

HAMMING DISTANCE; SWITCHING ACTIVITY;

DIGITAL SIGNAL PROCESSING;

EID: 0038825175     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20030347     Document Type: Article

References (13)

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