Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 4, 1999, Pages 492-497

  Masselos, K ^a   Merakos, P ^a   Stouraitis, T ^a   Goutis, C E ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

Digital signal processing; High level synthesis; Low power consumption; Low power design; Sum of product computation

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; ELECTRIC NETWORK SYNTHESIS;

SUM-OF-PRODUCT COMPUTATION;

DIGITAL SIGNAL PROCESSING;

EID: 0033280145     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.805757     Document Type: Article

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