A low power FIR filtering core

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 271-275

  Erdogan, A T ^a   Hasan, M ^a   Arslan, T ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; FIR FILTERS; MULTIPLYING CIRCUITS; RANDOM ACCESS STORAGE;

COEFFICIENT ORDERING; FIR FILTERING CORE; POWER REDUCTION;

LOGIC DESIGN;

EID: 0034775040     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Circuit techniques for CMOS low-power high-performance multipliers
2. Algorithms for low power and high speed FIR filter realisation using differential coefficients
3. Search-based wordlength optimisation for VLSI/DSP synthesis
4. Low power realisation of FIR filters using multirate architectures
5. Low power digital filtering using approximate processing
6. Low power implementation of linear phase FIR filters for single multiplier CMOS based DSPs
7. Low-power realization of FIR filters on programmable DSP's
8. Low power synthesis of sum-of-products computation