A single chip low power asynchronous implementation of an FFT algorithm for space applications

Proceedings - 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 1998-March, Issue , 1998, Pages 216-223

  Hunt, B W ^a   Stevens, K S ^a,b   Suter, B W ^a   Gelosh, D S ^a  

^a Air Force Institute of Technology   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; DISCRETE FOURIER TRANSFORMS; INTEGRATED CIRCUIT MANUFACTURE;

APPLICATION-SPECIFIC ARCHITECTURES; BOOTH MULTIPLIERS; CIRCUIT DESIGNS; DESIGN METHODOLOGY; FFT PROCESSORS; HIGH THROUGHPUT; LAYOUT EXTRACTION; LOW POWER IMPLEMENTATION;

SPACE APPLICATIONS;

EID: 0038019325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1998.666507     Document Type: Conference Paper

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