A true single-phase 8-bit adiabatic multiplier

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 758-763

  Kim, Suhwan ^a   Ziesler, Conrad H ^b   Papaefthymiou, Marios C ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b The Department of Civil and Environmental Engineering   (United States)

Author keywords

Adiabatic logic; Clock generator; CMOS; Dynamic logic; Low energy; Low power; Multiplier; SCAL; SCAL D; Single phase; VLSI

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ENERGY DISSIPATION; FREQUENCIES; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; WAVEFORM ANALYSIS;

ADIABATIC MULTIPLIERS; POWER CLOCK WAVEFORMS;

MULTIPLYING CIRCUITS;

EID: 0034841989     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156238     Document Type: Article

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