Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: Its tradeoff with gate capacitance

IEEE Transactions on Electron Devices

Volumn 50, Issue 2, 2003, Pages 433-439

  Fan, Yang Yu ^a   Xiang, Qi ^b   An, Judy ^b   Register, Leonard F ^c   Banerjee, Sanjay K ^c  

^a Lovoltech Inc   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

Gate capacitance; Gate current; High K gate stack; Semiconductor device modeling

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; INSULATING MATERIALS; LEAKAGE CURRENTS; NITRIDES; PERMITTIVITY; SEMICONDUCTOR DEVICE MODELS; SILICON COMPOUNDS;

GATE CAPACITANCE;

GATES (TRANSISTOR);

EID: 0038394712     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.809433     Document Type: Article

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