A new reasoning scheme for efficient redundancy addition and removal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 7, 2003, Pages 945-952

  Chang, Chih Wei Jim ^a   Hsiao, Ming Fu ^a,b   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Logic restructuring; Logic synthesis; Physical synthesis; Timing optimization

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; THEOREM PROVING;

LOGIC RESTRUCTURING; REDUNDANCY ADDITION AND REMOVAL;

LOGIC DESIGN;

EID: 0038105314     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.814239     Document Type: Article

References (16)

1. R. Brayton, G. Hachtel, and A. Sangiovanni-Vincentelli, "Multilevel logic synthesis," Proc. IEEE, vol. 78, pp. 264-300, Feb. 1990.
2. S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, "Perturb and simplify: multi-level boolean network optimizer," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1494-1504, Dec. 1996.
3. S.-C. Chang, L.P.P.P. Van Ginneken, and M. Marek-Sadowska, "Circuit optimization by rewiring," IEEE Trans. Comput., vol. 48, pp. 962-970, Sept. 1999.
4. ____, "Fast Boolean optimization by rewiring," in Proc. Int. Conf. Computer-Aided Design, Nov. 1996, pp. 262-269.
5. S.-C. Chang, K.-T. Cheng, N. S. Woo, and M. Marek-Sadowska, "Post-layout logic restructuring using alternative wires," IEEE Trans. Computer-Aided Design, vol. 6, pp. 587-596, June 1997.
6. S.-C. Chang and M. Marek-Sadowska, "Perturb and simplify: Optimizing circuits with external don't cares," in Proc. Design Automation Test Conf. Eur., 1996, pp. 402-406.
7. L. A. Entrena and K.-T. Cheng, "Combinational and sequential logic optimization by redundancy addition and removal," IEEE Trans. Computer-Aided Design, vol. 14, pp. 909-916, July 1995.
8. L. A. Entrena, J. A. Espejo, E. Olias, and J. Uceda, "Timing optimization by an improved redundancy addition and removal technique," in Proc. Eur. Design Automation Conf., 1996, pp. 342-347.
9. R. C-Y. Huang, Y. Wang, and K.-T. Cheng, "Libra-a library-independent framework for post-layout performance optimization," in Proc. Int. Symp. Physical Design, Apr. 1998, pp. 135-140.
10. M. A. Iyer and M. Abramovici, "FIRE: A fault-independent combinational redundancy identification algorithm," IEEE Trans. Very Large Scale Integrated Syst., vol. 4, pp. 295-301, June 1996.
11. Y.-M. Jiang, A. Krstic, K.-T. Cheng, and M. Marek-Sadowska, "Post-layout logic restructuring for performance optimization," in Proc. Design Automation Conf., 1997, pp. 662-665.
12. T. Kirkland and M. R. Mercer, "A topological search algorithm for ATPG," in Proc. Design Automation Conf., June 1987, pp. 502-508.
13. W. Kunz, D. Stoffel, and P.R. Menon, "Logic optimization and equivalence checking by implication analysis," IEEE Trans. Computer-Aided Design, vol. 16, pp. 266-281, Mar. 1997.
14. W. Kunz and D. Pradhan, "Recursive learning: a new implication technique for efficient solutions to CAD problems: test, verification and optimization," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1143-1158, Sept. 1994.
15. K. McElvain., LGSynth93 Benchmark Set: Version 4.0 [Online] Available: http://zodiac.cbl.ncsu.edu/CBL_Docs/lgs93.html
16. J. P. Roth, "Diagnosis of automata failures: a calculus and a method," IBM J. Res. Develop., vol. 10, pp. 278-291, 1966.