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Volumn , Issue , 2002, Pages 165-173

Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip

Author keywords

Automatic Layout Generation; Domain Specific FPGA; Standard Cells; System on a Chip

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036385566     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/503048.503073     Document Type: Conference Paper
Times cited : (29)

References (11)
  • 2
    • 4244104636 scopus 로고    scopus 로고
    • release IC 4.4.5
    • Cadence Design Systems, Inc., "Openbook", version 4.1, release IC 4.4.5, 1999.
    • (1999) Openbook, version 4.1
  • 6
    • 0034174187 scopus 로고    scopus 로고
    • PipeRench: An architecture and compiler for reconfigurable computing
    • April
    • Goldstein, S., Schmit, H., Budiu, M., Cadambi, S., Moe, M and Taylor, R. "PipeRench: An Architecture and Compiler for Reconfigurable Computing", IEEE Computer, Vol. 33, No. 4, pp 70-77, April 2000.
    • (2000) IEEE Computer , vol.33 , Issue.4 , pp. 70-77
    • Goldstein, S.1    Schmit, H.2    Budiu, M.3    Cadambi, S.4    Moe, M.5    Taylor, R.6
  • 10
    • 0010621353 scopus 로고    scopus 로고
    • Tanner Research, Inc., "Tanner CES Products", http://www.tanner.com/CES/products/files_now/dit_std_cell.htm.
    • Tanner CES Products


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.