Placement and Routing Tools for the Triptych FPGA

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 3, Issue 4, 1995, Pages 473-482

  Ebeling, Carl ^a   McMurchie, Larry ^a   Hauck, Scott A ^a   Burns, Steven ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ALGORITHMS; ARRAYS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; LOGIC DESIGN; SIMULATED ANNEALING;

FIELD PROGRAMMABLE GATE ARRAYS; PLACEMENT ALGORITHM; ROUTING ALGORITHM; TRIPTYCH ARCHITECTURE;

LOGIC GATES;

EID: 0029534183     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.475966     Document Type: Article

References (20)

1. C. Sechen and K. Lee, “An improved simulated annealing algorithm for row-based placement,” in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1987, pp. 478–481.
2. Xilinx, Inc., XACT Development System Reference Guide, Jan. 1993.
3. Algotronix Ltd., CAL1024 Preliminary Datasheet, 1991.
4. N. Togawa, M. Sato, and T. Ohtuski, “A simultaneous placement and global routing algorithm for field-programmable gate arrays,” presented at FPGA94, Berkeley, CA, 1994.
5. J. Beetem, “Simultaneous placement and routing of the LABYRINTH reconfigurable logic array,” Int. Workshop on Field-Programmable Logic and Appli., Oxford, England, 1991, pp. 232–243.
6. C. Lee, “An algorithm for path connections and its applications,” IRE Trans. Electron. Comput., vol. EC-10, 1961, pp. 346–365.
7. E. Kuh and M. Marek-Sadowska, “Global routing,” in Layout Design and Verification, T. Ohtsuki, Ed, New York: Elsevier Science, 1986, pp. 169–198.
8. R. Linsker, “An iterative-improvement penalty-function-driven wiresystem,” IBM J. Res. Develop., vol. 28, Sept. 1984, pp. 613–624.
9. J. Cohn, D. Garrod, R. Rutenbar, and L. Carley, “KOAN/ANAGRAM II: New tools for device-level analog placement and routing,” IEEE J. Solid-State Circuits, vol. 26, pp. 330–342, Mar. 1991.
10. D. Hill, “A CAD system for the design of field programmable gate arrays,” in Proc. 28th Design Automation Conf., June 1991, pp. 187–192.
11. M. Palczewski, “Plane parallel maze router to FPGAs,” in Proc. 29th Design Automation Conf, June 1992, pp. 691–697.
12. S. Brown, J. Rose, and Z. Vranesic, “A detailed router for field-programmable gate arrays,” IEEE Trans. on Computer-Aided Design, vol. 11, no. 5, pp. 620–628, May 1992.
13. J. Frankle, “Iterative and adaptive slack allocation for performance-driven layout and FPGA routing,” in Proc. 29h Design Automation pp. 536–542. Conf, June 1992.
14. L. McMurchie and C. Ebeling, “WireC tutorial and reference manual,” UW Dep. of CS&E TR#94-09-09, Sept. 1994.
15. G. Borriello, C. Ebeling, S. Hauck, and S. Burns, “The triptych FPGA architecture,” IEEE Trans. VLSI Syst., see this issue, pp. 491–501.
16. R. Nair, “A simple yet effective technique for global wiring,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 165–172, Mar. 1987.
17. H. Takahishi and A. Matsuyama, “An approximate solution Steiner problem in graphs,” Japonica, vol. 24, pp. 573–577, 1980.
18. Programmable Electronics Performance Corp., PREP PLD Benchmark Suite #1, Oct. 1992.
19. “LGSynth93 benchmark set,” in 1993 Int. Logic Synthesis Workshop, May 1993.
20. Sentovich et system of EE & CS, Univ. of California, Berkeley, CA, Electron. Res. Lab. Memo. UCB/ERL M92/41, May 1992.