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Volumn , Issue , 2003, Pages 230-240

Parallelism in the front-end

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC PROGRAMMING; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SEQUENTIAL MACHINES; THROUGHPUT;

EID: 0037670374     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/859618.859645     Document Type: Conference Paper
Times cited : (12)

References (22)
  • 12
    • 0038702894 scopus 로고    scopus 로고
    • ALTO: A link-time optimizer for the DEC alpha
    • Technical Report TR98-14, University of Arizona, September
    • R. Muth, S. Debray, S. Watterson, and K. de Bosschere. ALTO: A Link-Time Optimizer for the DEC Alpha. Technical Report TR98-14, University of Arizona, September 1998.
    • (1998)
    • Muth, R.1    Debray, S.2    Watterson, S.3    De Bosschere, K.4
  • 14
    • 0003696135 scopus 로고    scopus 로고
    • Critical issues regarding the trace cache fetch mechanism
    • Technical Report CSE-TR-335-97, Department of Electrical Engineering and Computer Science, University of Michigan, May
    • S. J. Patel, D. H. Friendly, and Y. N. Patt. Critical Issues Regarding the Trace Cache Fetch Mechanism. Technical Report CSE-TR-335-97, Department of Electrical Engineering and Computer Science, University of Michigan, May 1997.
    • (1997)
    • Patel, S.J.1    Friendly, D.H.2    Patt, Y.N.3
  • 16
    • 0003468743 scopus 로고
    • Dynamic flow instruction cache memory organized around trace segments independent of virtual address line
    • US Patent 5,381,533, March 30
    • A. Peleg and U. Weiser. Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line. US Patent 5,381,533, March 30, 1994.
    • (1994)
    • Peleg, A.1    Weiser, U.2
  • 22
    • 0031333687 scopus 로고    scopus 로고
    • Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order
    • Dec. 1-3
    • J. Stark, P. Racunas, and Y. N. Patt. Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. In Proceedings of the 30th Annual International Symposium on Microarchitecture, pages 34-43, Dec. 1-3, 1997.
    • (1997) Proceedings of the 30th Annual International Symposium on Microarchitecture , pp. 34-43
    • Stark, J.1    Racunas, P.2    Patt, Y.N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.