Quantifying the impact of current-sensing on interconnect delay trends

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 461-465

  Maheshwari, Atul ^a   Srinivasaraghavan, Srividya ^a   Burleson, Wayne ^a  

^a University of Massachusetts   (United States)

Author keywords

Chip coverage; Current sensing; Repeaters; Technology scaling

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; SEMICONDUCTOR DEVICE MANUFACTURE; TELECOMMUNICATION REPEATERS;

BERKELEY PREDICTIVE TECHNOLOGY MODELS; CHIP COVERAGE; CURRENT SENSING; DIFFERENTIAL CURRENT; INTERCONNECT CIRCUITS; SEMICONDUCTOR INDUSTRY ASSOCIATIONS; SIGNALING TECHNIQUES; TECHNOLOGY SCALING;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 0037654021     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158103     Document Type: Conference Paper

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