Trends and challenges in VLSI technology scaling towards 100nm

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 194-196

  Rusu, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 64549093087     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. P. Gelsinger, "Microprocessors for the New Millennium: Challenges, Opportunities and New Frontiers", ISSCC Digest of Technical Papers, 2001.
2. R. Chau et.al., "30nm Physical Gate Length CMOS Transistors with 1.0ps n-MOS and 1.7ps p-MOS Gate Delays", IEDM Tech. Digest, 2000.
3. S. Tyagi et.al., "A 130nm Generation Logic Technology Featuring 70nm Transistors, Dual Vt Transistors and 6 Layers of Cu Interconnects", IEDM Tech, Digest, 2000.