High fT 50-nm-gate lattice-matched InAlAs/InGaAs HEMTs

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2000, Pages 87-90

  Endoh, Akira ^a   Yamashita, Yoshimi ^a   Higashiwaki, Masataka ^a   Hikosaka, Kohki ^a   Mimura, Takashi ^a   Hiyamizu, Satoshi ^a   Matsui, Toshiaki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INDIUM ALUMINUM ARSENIDE;

ELECTRIC FREQUENCY MEASUREMENT; GATES (TRANSISTOR); LOW TEMPERATURE OPERATIONS; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING INDIUM GALLIUM ARSENIDE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0033706622     PISSN: 10928669     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (8)

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2. T. Enoki, M. Tomizawa, Y. Umeda, and Y. Ishii, "0.05-μm-Gate InAlAs/InGaAs High Electron Mobility Transistor and Reduction of Its Short-Channel Effects," Jpn. J. Appl. Phys. 33, pp. 798 - 803 (1994).
3. T. Suemitsu, T. Ishii, H. Yokoyama, Y. Umeda, T. Enoki, Y. Ishii, and T. Tamamura, "30-nm-Gate InAk/InGaAs HEMTs Lattice-Matched to InP Substrates," IEDM Tech. Dig., 1998, pp. 223 - 226.
4. T. Suemitsu, T. Ishii, H. Yokoyama, T. Enoki, Y. Ishii, and T. Tamamura, "30-nm-Gate InP-Based Lattice-Matched High Electron Mobility Transistors with 350 GHz Cutoff Frequency," Jpn. J. Appl. Phys. 38, pp. L154 - L156 (1999).
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6. S. R. Bahl and J. A. del Alamo, "Elimination of mesa-sidewall gate recessing," IEEE Electron Device Lett. 13, pp. 195 - 197 (1992).
7. G. Dambrine, A. Cappy, F. Heliodore, and E. Playeg "A New Method for Determining the FET Small-Signal Equivalent Circuit," IEEE Trans. Microwave Theory Tech. 36, pp. 1151 - 1159 (1988).
8. T. Enoki, K. Arai, and Y. Ishii, "Delay Time Analysis for 0.4- to 5-μm-Gate InAlAs-InGaAs HEMT's," IEEE Electron Device Lett. 11, pp. 502 - 504 (1990).