Novel asymmetric gate-recess engineering for sub-millimeter-wave InP-based HEMTs

IEEE MTT-S International Microwave Symposium Digest

Volumn 1, Issue , 2001, Pages 2159-2162

  Shinohara, Keisuke ^a   Matsui, Toshiaki ^a   Mimura, Takashi ^b   Hiyamizu, Satoshi ^c  

^a Ministry of Posts and Telecommunications   (Japan)

^b FUJITSU LABORATORIES LTD   (Japan)

^c OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC FIELDS; ELECTRIC RESISTANCE; ETCHING; GATES (TRANSISTOR); METALLORGANIC CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

ASYMMETRIC GATE RECESS ENGINEERING; SEMICONDUCTING INDIUM ALUMINUM ARSENIDE;

HIGH ELECTRON MOBILITY TRANSISTORS;

EID: 0035686258     PISSN: 0149645X     EISSN: None     Source Type: Journal    
DOI: 10.1109/MWSYM.2001.967342     Document Type: Article

References (4)

1. 30-nm-gate InP-based lattice-matched high electron mobility transistors with 350 GHz cutoff frequency
2. T 50-nm-gate InAlAs/InGaAs high electron mobility transisitors lattice-matched to InP substrates
3. 50-nm self-aligned-gate pseudomorphic AlInAs/GaInAs high electron mobility transisitors
4. T (>300 GHz) and their MMIC applications