A Physically-Based Built-in Spice Poly-Si TF" Model for Circuit Simulation and Reliability Evaluation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 139-142

  Chung, Steve S ^a   Chen, Darren C ^a   Cheng, C T ^a   Yeh, C F ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

POLYCRYSTALLINE MATERIALS; POLYSILICON; RELIABILITY; SPICE; THIN FILM TRANSISTORS; TIMING CIRCUITS; BIPOLAR TRANSISTORS; CARRIER CONCENTRATION; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; ELECTRON TRANSPORT PROPERTIES; ELECTRONIC DENSITY OF STATES; GRAIN BOUNDARIES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SOLID STATE OSCILLATORS;

'SPICE'; CIRCUIT RELIABILITY; DEGRADATION MODEL; DEVICE DEGRADATION; OPERATING REGIMES; PHYSICALLY BASED; POLY-SI TFTS; RELIABILITY EVALUATION; SIMULATION EVALUATION; V-MODEL;

GRAIN BOUNDARIES; THIN FILM TRANSISTORS;

ELECTRICAL STRESS; GRAIN BOUNDARY TRAP STATE; RING OSCILLATOR; TRAP DENSITY;

EID: 0030388125     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553140     Document Type: Conference Paper

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