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Volumn 47, Issue 4, 2003, Pages 721-726

Achieving the ballistic-limit current in Si MOSFETs

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; CMOS INTEGRATED CIRCUITS; ELECTRIC FIELD EFFECTS; SEMICONDUCTOR DOPING; SILICON;

EID: 0037394247     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(02)00330-1     Document Type: Article
Times cited : (8)

References (19)
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  • 2
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    • Vasileska, D.1    Schroder, D.K.2    Ferry, D.K.3
  • 8
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    • Arizona State University, Tempe, AZ, and Purdue University, West Lafayette, IN, February
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  • 9
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    • A high performance 180 nm generation logic technology
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    • A 1.2 V, 0.1 μm gate length CMOS technology: Design and process issue
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    • (1998) IEDM Tech. Dig. , Issue.DECEMBER , pp. 623-626
    • Rodder, M.1    Hattangady, S.2    Yu, N.3    Shiau, W.4    Nicollian, P.5
  • 11
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.