Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 19-22

  Huang, Xuejue ^b   Restle, Phillip ^a   Bucelot, Thomas ^a   Cao, Yu ^b   King, Tsu Jae ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CLOCKS; ELECTROMAGNETISM; INDUCTANCE; MICROPROCESSOR CHIPS; OPTIMIZATION;

INTERCONNECT MODELING;

INTERCONNECTION NETWORKS;

EID: 0036045268     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2002.1012758     Document Type: Article

References (4)

1. Inductance calculation in a complex integrated circuit environment
2. Layout techniques for minimizing on-chip interconnect self-inductance
3. Analysis of current crowding effects in multiturn spiral inductors
4. Full-wave PEEC time-domain method for the modeling of on-chip interconnects