Analytical performance models for RLC interconnects and application to clock optimization

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn 2002-January, Issue , 2002, Pages 353-357

  Huang, Xuejue ^a   Cao, Yu ^a   Sylvester, Dennis ^b   King, Tsu Jae ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of Michigan   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; VOLTAGE REGULATORS;

ANALYTICAL APPROACH; ANALYTICAL PERFORMANCE MODEL; CLOSED-FORM EXPRESSION; DESIGN OPTIMIZATION; INTERCONNECT OPTIMIZATION; PROPAGATION DELAYS; RLC INTERCONNECTS; VOLTAGE OVERSHOOT;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 27544471932     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158084     Document Type: Conference Paper

References (9)

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3. X. Huang, P. Restle, T. Bucelot, Y. Cao, and T-J. King, "Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design", IEEE Custom Integrated Circuits Conference (C1CC), pp. 19-22, 2002.
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7. Y.I. Ismai and E.G. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.8, (no.2), pp. 195-206, April 2000.
8. http://www.eecs.berkeley.edu/~xuejue/ASIC02.htm
9. P. Restle, T. McNamara, D. Webber, et al, "A Clock Distribution Method for Microprocessors", IEEE Journal of Solid-State Circuits, vol. 36, no. 5, pp.792-799, May 2001.