A novel parallel approach for quantum effect simulation in semiconductor devices

International Journal of Modelling and Simulation

Volumn 23, Issue 2, 2003, Pages 94-102

  Li, Yiming ^a,b   Chao, Tien Sheng ^a,b   Sze, Simon M ^a,b  

^a NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

C V curves; Monotone iterative method; MOS devices; Parallel divide and conquer algorithm; Quantum confinement effect; Schr dinger and Poisson equations; Semiconductor device simulation

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CURVE FITTING; POISSON EQUATION; QUANTUM THEORY;

QUANTUM CONFINEMENT EFFECTS;

MOS DEVICES;

EID: 0037270174     PISSN: 02286203     EISSN: None     Source Type: Journal    
DOI: 10.1080/02286203.2003.11442259     Document Type: Article

References (28)

1. 2 oxide<5nm thick films. Journal of Non-Crystalline Solids, 280 (1-3), 2001, 110-115.
2. A. Trellakis & U. Ravaioli, Computational issues in the simulation of semiconductor quantum wires, Computer Methods in Applied Mechanics and Engineering, 181 (4), 2000, 437-449.
3. Y. Omura & Y. Nakajima, Quantum mechanical influence and estimated errors on interface-state density evaluation by quasi-static C-V measurement, Solid-State Electronics, 44, 2000, 1511-1514.
4. M.G. Ancona, Simulation of quantum confinement effects in ultra-thin-oxide MOS structures, IEEE Journal of Technology on CAD, 1998, 1-17.
5. S.-H. Lo, D.A. Buchanan, & Y. Taur, Modeling and characherization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides, IBM Journal of Research and Development, 43(3), 1999, 327-337.
6. A. Pacelli, Self-consistent solution of the Schrödinger equation in semiconductor devices by implicit iteration, IEEE Transactions on Electron Devices, 44(7), 1997, 1169-1171.
7. S.I. Takagi & A. Toriumi, Quantitative understanding of inversion-layer capacitance in Si MOSFET's, IEEE Transactions on Electron Devives, 42(12), 1995, 2125-2130.
8. S.M. Sze, Semiconductor devices, physics and technology (New York: Wiley, 2002).
9. C.Y. Chang & S.M. Sze, ULSI devices (New York: Wiley & Sons, 2000).
10. Y. Li, S.-S. Chung, & J.-L. Liu, A novel approach for the two-dimensional simulation of submicron MOSFET's using monotone iterative method, Technical Proc. of the IEEE International Conf. on VLSI-TSA, Taipei, Taiwan, 1999, 27-30.
11. Y. Li, P. Chen, J.-L. Liu, T.-S. Chao, & S.M. Sze, Adaptive finite volume simulation of semiconductor devices on cluster architecture, in N. Mastorakis (Ed.), Recent advances in applied and theoretical mathematics (Athens: World Scientific and Engineering Society Press, 2000).
12. Y. Li, S.-S. Lin, S.-M. Yu, J.-L. Liu, T.-S. Chao, & S.M. Sze, Parallel dynamic load balancing for semiconductor device simulations on a linux cluster, Technical Proc. of the International Conf. on Modelling and Simulation of Microsystem (MSM 2001), Hilton Head Island, USA, 2001, 562-566.
13. K.-Y. Huang, Y. Li, C.P. Lee, & S.M. Sze, A Computational efficient method for HBT intermodulation distortions and two-tone characteristics simulation, in D. Tsoukalas and C. Tsamis (Eds.), Simulation of semiconductor processes and devices 2001 (Vienna: Springer-Verlag, 2001).
14. Y. Li, J.-L. Liu, T.-S. Chao, & S.M. Sze, A new parallel adaptive finite volume method for the numerical simulation of semiconductor devices, Computer Physics Communications, 142(1-3), 2001, 285-289.
15. Y. Li, A monotone iterative method for semiconductor device drift diffusion equations, WSEAS Transactions on Systems, 1(1), 2002, 68-73.
16. R.S. Varga, Matrix iterative analysis (New York: Springer, 2000).
17. I. Bar-On & B. Codenotti, A fast and stable parallel QR algorithm for symmetric tridiagonal matrices, Linear Algebra and Its Applications, 220, 1999, 63-95.
18. M. Gu & S.C. Eisenstat, A divide-and-conquer algorithm for the symmetric tridiagonal eigenproblem, SIAM Journal of Matrix Analysis and Application, 16(1), 1995, 172-191.
19. F. Tisseur & J. Dongarra, A parallel divide and conquer algorithm for the symmetric engenvalue problem on distributed memory architectures, SIAM Journal of Scientific Computing, 20(6), 1999, 2223-2236.
20. D.S. Watkins, QR-like algorithms for eigenvalue problems, Journal of Computational and Applied Mathematics, 123 (1-2), 2000, 67-83.
21. Y. Saad, Numerical methods for large eigenvalue problems (Manchester: Manchester University Press, 1992).
22. K. Dowd & C. Severance, High performance computing (Sebastopol: O'Reilly, 1998).
23. P.S. Pacheco, Parallel programming with MPI (San Francisco: Morgan Kaufmann, 1997).
24. R.W. Dutton & A.J. Strojwas, Perspectives on technology and technology-driven CAD, IEEE Transactions on CAD, 19(2), 2000, 1544-1560.
25. W. Liu, MOSFET models for SPICE simulation including BSIM3v3 and BSIM4 (New York: John Wiley & Sons, 2001).
26. L. Larcher, P. Pavan, F. Pellizzer, & G. Ghidini, A new model of gate capacitance as a simple tool to extract MOS parameters, IEEE Transactions on Electron Devices, 48(5), 2001, 935-945.
27. K. Hasnat, S. Murtaza, & A.F. Tasch, Jr., A manufacturing sensitivity analysis of 0.35μm. LDD MOSFET's, IEEE Transactions on Semiconductor Manufacturing, 7(1), 1994, 53-59.
28. N.D. Arora, E. Rios, & C.-L. Huang. Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance, IEEE Transactions on Electron Devices, 42(5-1), 1995, 935-943.